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Focus On:
Timing
Focus On: Timing
Timing is not hard -you just need to stay on the clock. Which clock and how it is synchronized can be a challenge especially when multiple sources are involved and tight timing constraints are imposed due to frequency, jitter and the length of transmission lines. Multisource clock-tree synthesis is an option for clock distribution, joining conventional clock-tree synthesis and clock mesh that is being utilized in more advanced designs. This and other topics like the difference between jitter and noise provide insight into system clock design and distribution.
What’s Inside
What’s the Difference Between CTS, Multisource CTS, and Clock Mesh?
What’s the Difference Between Jitter and Noise?
Jitter Simplified
PCI Express Clock Generators, Buffers Prepare for Next Generation
Bill Wong
Content Director, Electronic Design & MWRF
Bill Wong covers Digital, Embedded, Systems and Software topics at Electronic Design. He writes a number of columns, including Lab Bench and alt.embedded, plus Bill’s Workbench hands-on column. Bill is a Georgia Tech alumni with a B.S. in Electrical Engineering and a master’s degree in computer science for Rutgers, The State University of New Jersey.
He has written a dozen books and was the first Director of PC Labs at PC Magazine. He has worked in the computer and publication industry for almost 40 years and has been with Electronic Design since 2000. He helps run the Mercer Science and Engineering Fair in Mercer County, NJ.
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